Yosys Manual

A quick first-steps tutorial can be found in the README file.

Edif netlist format. EDIF, EDIF is a complex format that can include hierarchical information. Parsing such a file can be quite slow, making opening an XJTAG project EDIF (Electronic Design Interchange Format) is a vendor-neutral format based on S-Expressions in which to store Electronic netlists and schematics.

Electronic Data Interchange Format file. An industry standard file format for specifying a design netlist.
Writeedif - write design to EDIF netlist file. Writeedif options filenameWrite the current design to an EDIF netlist file.top topmodule set the specified module as design top module -nogndvcc do not create 'GND' and 'VCC' cells. (this will produce an error if the design contains constant nets. Use 'hilomap' to map to custom constant drivers first) -gndvccy create 'GND' and 'VCC'.
Yosys is controlled using synthesis scripts. For example, the following Yosys synthesis script reads a design (with the top module mytop) from the verilog file mydesign.v, synthesizes it to a gate-level netlist using the cell library in the Liberty file mycells.lib and writes the synthesized results as Verilog netlist to synth.v.

The Yosys manual can be downloaded here (PDF).

Edif Netlist File Format Examples

Support

The best places to ask questions are the Yosys Subreddit, Stack Overflow and#yosys on freenode.The best place to report a bug is on GitHub. File

Presentation Slides

This presentation slides cover a wide range of topics related to Yosys. (The LaTeX source is part of the Yosys source distribution. Fell free to adapt the slides as needed.)

Application Notes

Papers and other Publications

Clifford Wolf, Johann Glaser. Yosys - A Free Verilog Synthesis Suite.In Proceedings of Austrochip 2013.[download pdf]
Johann Glaser and Clifford Wolf. Methodology and Example-Driven InterconnectSynthesis for Designing Heterogeneous Coarse-Grain ReconfigurableArchitectures. In Jan Haase, editor, Models, Methods, and Tools forComplex Chip Design. Lecture Notes in Electrical Engineering. Volume 265,2014, pp 201-221. Springer, 2013.[download pdf]

In papers and reports, please refer to Yosys as follows: Clifford Wolf.Yosys Open SYnthesis Suite. http://www.clifford.at/yosys/, e.g. using thefollowing BibTeX code:

Command Reference

abcuse ABC for technology mapping
addadd objects to the design
aigmapmap logic to and-inverter-graph circuit
alumaccextract ALU and MACC cells
anlogic_determine_initAnlogic: Determine the init value of cells
anlogic_eqnAnlogic: Calculate equations for luts
assertpmuxadds asserts for parallel muxes
async2syncconvert async FF inputs to sync circuits
attrmaprenaming attributes
attrmvcpmove or copy attributes from wires to driving cells
blackboxconvert modules into blackbox modules
bugpointminimize testcases
cda shortcut for 'select -module <name>'
checkcheck for obvious problems in the design
chformalchange formal constraints of the design
chparamre-evaluate modules with new parameters
chtypechange type of cells in the design
cleanremove unused cells and wires
clk2fflogicconvert clocked FFs to generic $ff cells
connectcreate or remove connections
connwrappersmatch width of input-output port pairs
coolrunner2_sopbreak $sop cells into ANDTERM/ORTERM cells
copycopy modules in the design
coverprint code coverage counters
cutpointadds formal cut points to the design
debugrun command with debug log messages enabled
deletedelete objects in the design
deminoutdemote inout ports to input or output
designsave, restore and reset current design
determine_initDetermine the init value of cells
dff2dffetransform $dff cells to $dffe cells
dff2dffsprocess sync set/reset with SR over CE priority
dffinitset INIT param on FF cells
dfflibmaptechnology mapping of flip-flops
dffsr2dffconvert DFFSR cells to simpler FF cell types
dumpprint parts of the design in ilang format
echoturning echoing back of commands on and off
ecp5_ffinitECP5: handle FF init values
edgetypeslist all types of edges in selection
equiv_addadd a $equiv cell
equiv_inductproving $equiv cells using temporal induction
equiv_makeprepare a circuit for equivalence checking
equiv_markmark equivalence checking regions
equiv_miterextract miter from equiv circuit
equiv_optprove equivalence for optimized circuit
equiv_purgepurge equivalence checking module
equiv_removeremove $equiv cells
equiv_simpletry proving simple $equiv instances
equiv_statusprint status of equivalent checking module
equiv_structstructural equivalence checking
evalevaluate the circuit given an input
exposeconvert internal signals to module ports
extractfind subcircuits and replace them with cells
extract_counterExtract GreenPak4 counter cells
extract_fafind and extract full/half adders
extract_reduceconverts gate chains into $reduce_* cells
flattenflatten design
flowmappack LUTs with FlowMap
fmcombinecombine two instances of a cell into one
freduceperform functional reduction
fsmextract and optimize finite state machines
fsm_detectfinding FSMs in design
fsm_expandexpand FSM cells by merging logic into it
fsm_exportexporting FSMs to KISS2 files
fsm_extractextracting FSMs in design
fsm_infoprint information on finite state machines
fsm_mapmapping FSMs to basic logic
fsm_optoptimize finite state machines
fsm_recoderecoding finite state machines
greenpak4_dffinvmerge greenpak4 inverters and DFF/latches
helpdisplay help messages
hierarchycheck, expand and clean up design hierarchy
hilomaptechnology mapping of constant hi- and/or lo-drivers
historyshow last interactive commands
ice40_braminitiCE40: perform SB_RAM40_4K initialization from file
ice40_dspiCE40: map multipliers
ice40_ffinitiCE40: handle FF init values
ice40_ffssriCE40: merge synchronous set/reset into FF cells
ice40_optiCE40: perform simple optimizations
ice40_unlutiCE40: transform SB_LUT4 cells to $lut cells
insbufinsert buffer cells for connected wires
iopadmaptechnology mapping of i/o pads (or buffers)
jsonwrite design in JSON format
logprint text and log files
lslist modules or objects in modules
ltpprint longest topological path
lut2muxconvert $lut to $_MUX_
maccmapmapping macc cells
memorytranslate memories to basic cells
memory_brammap memor